Electronic circuitry provides complex functionality that is proving ever more useful. In one common form, circuitry is formed on a semiconductor or other substrate using micro-fabrication processing technology. Typically, circuits with small feature dimension sizes are not designed to carry large amounts of current. So long as the voltage range at any given node does not extend outside of its designed range, these currents remain relatively low and the circuitry will typically operate as designed. However, if the voltage range at any given node extends out of its designed range, a condition of Electrical OverStress (EOS) may occur.
For example, most common semiconductor fabrication processes use substrate or bulk semiconductor with different dopants implanted into certain regions of the substrate. These implant regions define unique electrical characteristics that are important or essential for circuit functionality. Thus, EOS experienced at any of the implant regions may adversely impact circuit performance. Another area where EOS may adversely affect performance is in the interlayer dielectrics, which have voltage limitations as well. Driving a circuit outside of its normal operating range can often temporarily disable performance of the circuit, reduce the operational lifetime of the circuit, or even immediately destroy the circuit. EOS can take many forms, but commonly takes the form of Electro Static Discharge (ESD) events.
Many current protection structures have been designed that are suitable for dissipating current to or from corresponding critical circuit nodes in order to provide protection to corresponding circuitry. Conventionally, a more likely source of excess current is on the pads of integrated circuits, where externally generated voltages and currents are applied to the integrated circuit. To deal with the potential of EOS events occurring at a given pad, conventional circuits often have current protection structures at or near each pad.
Conventionally, each current protection structure discharges current to a power domain that is local to its respective core circuitry. This is true regardless of whether the protection structure is uni-directional (i.e., a protection structure that triggers current discharge only of one of the positive or negative excessive voltage condition) or bi-directional (i.e., a protection structure that triggers current discharge of both positive and negative excessive voltage conditions). This network of EOS protection structures results in complex metallization schemes with large pad structures with multiple circuit-wide interconnection busses. The complexity of such metallization requires significant space on the integrated circuit. To exacerbate the problem, the complex metallization causes significant voltage drops across the metallization, which is often countered by using strategically placed voltage clamps distributed throughout the circuit. Such distributed voltage clamps, of course, require additional circuit space.
Currently, a circuit may operate in multiple voltage domains. For instance, mixed signal integrated circuits are in widespread use. Such mixed signal integrated circuits operate using digital voltage and current signals (thus operating in the digital voltage domain) as well as analog voltage and current signals (thus operating in the analog voltage domain). Furthermore, there are often components of a circuit that operate using different useful voltages. For instance, there may be high voltage components that high voltages may be acceptably applied to (thus operating in a high voltage domain), whereas other components may be lower voltage components for which such high voltages may represent a definitive EOS condition (thus operating in a lower voltage domain). The use of mixed signal integrated circuits complicates the metallization complexity with the need for signal isolation based on voltage range or signal type. Typical circuitry has pads for a particular voltage domain in one portion of the circuit to provide signal isolation. These complex networks of protection structures and bussing increase the risk for signal corruption, excessive pad loading, leakage current, and decreased durability when exposed to EOS events.